1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for preventing abnormal capacitor formations by introducing an offline edge-bead rinsing (EBR) in the fabrication of dynamic random access memory (DRAM).
2. Description of the Prior Art
Manufacturing of semiconductor substrates encompasses hundreds of different process steps. The steps involve creating patterns, introducing dopant, and depositing films on a silicon substrate repetitively throughout the manufacturing process to form integrated structures. Because the various structures that are built on a substrate or a wafer are serial in nature, that is, that they are built one on top of another in a sequential manner, it becomes very important that each layer of structure is substantially defect free before the next one is placed thereon.
Defects are generally caused when an unwanted particulate matter unintentionally lands between features on a layer and "bridges" or connects them, and therefore, disables them by "shorting" under certain conditions; or when an unwanted particulate matter lands on a feature, and disables it by creating an unwanted "open" in the circuitry; or when an abnormal capacitor forms and collapses during a DRAM fabrication. Normally, as each layer is deposited and then essentially trimmed back from the edge of the wafer through a judicious use of mask and etching, and/or edge-bead rinsing (EBR) and later sealed by wafer edge exposure (WEE). The abnormal structures of capacitors are still formed at the edge of wafers that later peel or break up to form particulate matter and fine dust.
FIG. 1A illustrates a semiconductor structure formed over a silicon substrate 10. The semiconductor structure comprises a bit line 12, a gate electrode 14, a source/drain region 16, and an isolation region 18. Furthermore, there formed a dielectric layer 20 in between the semiconductor structure and a conductive layer 22. An abnormal photoresist mask 24 having gradually decreased pattern is formed on top of the conductive layer 22 after an online EBR and/or a WEE process. A portion of the conductive layer that is not covered by the photoresist mask is then etched to form a lower capacitor electrode 26 and to expose a portion of the dielectric layer 20, like what is shown in FIG. 2B. Wherein, capacitor 26A and 26B are normal patterns, capacitor 26C and 26D are abnormal patterns with decreased in width. These abnormal capacitors are easy to peel off and collapse, eventually ending up with the worst situation shown in FIG. 1C, where capacitor 26C and 26D are collapsed toward capacitor 26B. Hence, the overall DRAM fabrication ends up with defects in DRAM cells and a drop-off in yield.